Thomas Allsup

GD&T Mini-Seminar

Discussion created by Thomas Allsup on Feb 21, 2012

This Friday, February 24, 2012, from 1:00PM to 5:00PM, we will be holding a mini-GD&T Seminar for $100 per participant at our Richardson, TX office - contact Thomas Allsup for more info at tallsup@anidatech.com - there are three seats available.

 

Geometric Dimensioning and Tolerances (GD&T) is the common language used to describe the allowable variances of manufactured feature sizes, shapes, and locations beyond that which can be controlled by regular rectilinear and angular dimensions and tolerances.  Semiconductor component and socket manufacturer drawings both use GD&T to insure their respective components fit and function mechanically together.  The “How to Spell GD&T” tutorial previously presented at BiTS provided a detailed primer of how to read GD&T symbols on drawings and provides an introduction to this tutorial.  This new tutorial is presented in three sections: Section one provides a highly abbreviated “How to Spell GD&T” review of the fundamentals of GD&T, Section two explains the first changes to the ASME Y14.5 standard in fifteen years particularly where those changes impact semiconductor professionals, and Section three contains a series of public domain semiconductor component drawings that will be carefully dissected to explain how GD&T was used correctly and incorrectly.

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