Bill makes a good suggestion about jedec's modeling standards. Before our recent acquisition of the electronics module, I was in the same situation as you, and I'll describe what I did as a work around. You're on the right track with modeling the chip as a combination of layers, but I suggest 2 layers instead of 3. As a starting point, get a hold of the chip manufacturer's data sheet, which should contain their published value for the junction-to-case thermal resistance.
Make your two layers of equal thickness, each one half the actual thickness of the chip. By taking into account the actual footprint of the chip (cross sectional area of the lower layer) you can create a new material whose thermal conductivity gives you the same published junction to case resistor from the manufacturer. That is, Rthermal = layer thickness/ (conductivity*area). Do the same for the top layer to mimic the junction to top resistance. If the manufacturer doesn't publish a junction to top resistance, make the top layer's conductivity very low, which will give you a high, conservative value for the junction-to-top resistance. this means any heat will flow from the junction through the chip's bottom layer into the board.
Lastly, apply the heat dissipation onto the top surface of the bottom layer. The heat will then flow from that surface to the bottom and top layers while obeying the manufacturer's junction to case (and top) resistances.
Hope this helps,
that's good advice that I didn't have time for when I did my last post. I do recommend you read the standards I mentioned - it will give you a good overview of teh approaches used. Key thing is to just approximate the package to give you the right reistance in whatever directions are of interest. The other thing is how close are you trying to get? I found that eventhe supplied chip resistnces inthe electronics modue are pretty conservative...I have modified versions to match data sheets more closely. If all else fails 18W/m-K is not a bad place to be.......
Currently, we have a product that we have done extensive real world thermal testing on. My first goal is to try and remodel this so that I have a good idea that the way I have the simulation setup is fairly accurate. My goal is to be within about 5 degrees C of the real world measured temeratures. Right now I am about 15 degrees C too high. Once I feel confident with the results I will start modeling our new products. I did download some of the files from the JEDEC website and will review these. I also appreciate David's advice and will try that on my next simulation.
I have the same problem, however I am using the 2R Components function.
Can you tell me if you succeeded in solving your problem ?
sebastian, being that this is a year old, it is unlikely that you'll get a response. where are you stuck at this point?
Thank you for your answer.
I am still trying to simulate my motherboard with two DDR3s and a flip chip.
I used 2Rs component for my flip chip (which isn't very accurate) and tried to play with the values of Rth j-c and Rth j-b but the results in general, even for the DDR3s only, seems too high.
The company I work for hired a specialized company to do the simulation for them and, compared to their results, mine are 20°C higher.
They even sent us the values they used for the Rth so we have exactly the same configuration but they use a different software, I don't know which one though.
However, when I do the math with the formula:
Tj = Tb + (Theta j-b x P), my results are very close but further from the reality testings.
Maybe there might be something wrong with the Power Dissipation that I am using..
I joined a screenshot of the design and values used..
I will try to design as Jason did and will let you know how it goes.
Thanks again and best regards.
I received results that I was fairly happy with. My best suggestion would be to have a real world example that you can then model and see how close you can get the results to reality. Then you can start working on a new design. There were a lot of variables to play with in order to get my model as accurate as possible. I modeled my chip as four separate parts and then assigned different materials to each of them. The four sides of my part were insulated and were 0.1mm thick, and for the solid material I used insulator. I then had a thin layer at the bottom of the chip that was tin bearing bronze, a middle section that was very thermally conductive like copper, and then a top layer (I don't have a good answer for what material to apply, but it should be less thermally conductive than the bottom and middle sections). The trick was to use the correct materials and thicknesss that most accurately represent your chip. Unfortunately, I don't have a very concrete answer to exactly which materials and thicknesses to use. I then set my middle section as my heat source, and set a goal of max temperature and then selected the middle section to follow.
If anyone has any better suggestions, I would be glad to hear them. I was able to get results that I was happy with, but it took a lot of tweaking.
Thank you for your answer.
I will try this today for my simulation and use differents thicknesses.
Did you add any contact resistance in your model or only materials ?