I generated board files (Gerber x2s) for a design and the CM is saying the board files show multiple layers have the same physical location -and- that there are numerous instances of less than 3 mil space/trace. There are -no- such spacings space/trace and the stack looks fine. Someone explain to me what is going on, this is pretty strange. I need to get these files to the Contract Manufacturer asap.
Thanks Injy,
So okay I see the artifacts now. What a mess. WHO in their right sane mind would design EDA software that trashed its own pcbs with tiny invisible artifacts you have to go to B&W and zoom in to even see? Inexcusable bad software design. Not your fault, but it is. Is there a way to select all of this software-generated MESS and delete them at once or is it now going to be an hour of deleting these stubs?
Also, the software doesn't seem to want to let me SELECT these tiny artifacts to delete them. What is the simplest way to do that?
Thank you, but this is frustrating, and these stubs should have a cleaner or some such thing that runs post layout during the Output phase or something. Putting near-invisible artifact stubs all over someones 8 or 10 layer GOOD DESIGN is inexcusable software laziness.
-Jeffrey
Hello Jeffrey,
I totally understand and I would recommend to escalate your request to your VAR so they can submit a ticket for improvements. Stubs should be an optional feature in the software that can be applied thru the DRC utility.
Unfortunately, now these must be cleaned up manually.
Regards!
Injy
Okay, I see. However these are all LOCKED as well...how to unlock for a clear/delete?
FYI I have just migrated to using SWPCB so questions may seem a little basic. However, I have designed several thousand analog and digital boards using several other EDAs like Ultiboard, PADS, CircuitMaker, Older versions of Altium, Eagle , and a list as long as your arm of others for many years (30?)
So , that said, the basics are necessarily just like about any other EDA software and thats no problem whatsoever. The only problem is for me, I have deadlines which disallow me to go through volumes of SWPCB documentation just to find one simple function/action set I need sometimes. Of course , the shortcuts are different from Altium proper, but the menu system itself in SWPCB is very intuitive and there's a host of benefits and features that I really like. I function as the Senior R&D Engineer with a robotic prosthetic corporation right now that uses SolidWorks exclusively, so the connectivity between the Mechanical, Electrical, and PCB systems is very useful.
I need , simply, to be aware of any potentially disastrous defaults in the design rule set and change them if possible in order to avoid the artifact/stub problem I encountered and other equally bizarre things that crop up in ALL EDAs not just SWPCB.
I don't want to come across as critical , please don't misunderstand me on that. Just help me to get rid of these pesky stubs, and tell me how to avoid these in the future. This -one- glitch cost me hours of work and will continue to do so until they are completely eradicated from my good 8-layer board design.
Thanks,
Jeffrey
Hello Jeffrey,
I am sorry to hear about this issue. Possible that those might be tiny stubs that were inadvertently placed during routing. To better examine the PCB, change the View to Draft mode. To do so, press L on the key board to access the View configurations dialog then go to the Show/Hide tab and change all to Draft. This will change the display of all objects to draft instead of full to better examine if you have any stubs or net antenna. You can also run the Net antenna design rule in the Design Rules window, under the Manufacturing category, there should be one by default already , make sure that it is enabled. You can adjust the net antenna length.
http://documentation.solidworkspcb.com/display/SWPCB/PCB_Dlg-Form_DesignRules_NetAntennae((Net%20Antennae))_PW/?help-data=PCB.Dlg.Form_DesignRules.Net%20Antennae
Pull the Rules &Violations panel from the View menu, select the Net antenna, right click and choose Run DRC Rule Class Net Antenna.
The violations section with the panel will display will the violations. If you click on the violation it will highlighted it and zoom in depending on your setting of the panel. (please see screen shots attached).
Hope this helps.
Injy Gadalla
Territory Technical Manager, SOLIDWORKS PCB