The adn8834 is designed to operate around 90% efficiency, depending on the effective resistance of the TEC. If you have a supply voltage of 5V and a TEC current of 400mA, the supplied power at the TEC is much less than 2watts. Most of the power is delivered to the load and the TEC itself dissipates very little.
So....how are you estimating the power at the TEC? What is the supply voltage, what is the tec current and what is the tec resistance?
Thank you for the insight. The supply parameters are measured as 5V and 175 mA and the TEC resistance is 2 Ohms. So, If i assume 90% efficiency the temperature raise becomes limited to 35 degrees celcius, which is nearer to the actual test results.
But I have a few more doubts out of my own curiosity,
* Will this efficiency be applicable to all the ICs used in a board (ie 90% efficiency).
* If only 10% of the power supplied, what happens to the rest of the energy supplied? Will that be supplied to the load connected or will it dissipate as heat somewhere else (but not in the IC)?
#1. This is not a guessing game. The electrical engineer should be able to measure the power going into the controller. This is not a power supply (correct?) so essentially all power going in will be converted to heat. Also consider duty cycle - average the power over time.
DeltaT = Q * R
DeltaT is temperature rise (C)
Q is power (2.6 W)
R is resistance (the resistance you have is from the junction to the PCB) 37 W/C
DeltaT = 37 * 2.6 = 96.2°C rise junction to PCB (now you need to add in the temperature rise from the PCB to the air). The convection resistance PCB to air is a difficult calculation due to the complexity of heat spreading. Refer to a text book on electronics cooling on how to calculate this. Also the above calculation dose not account for the jc path.
Add the resistance Rjb and Rjc as shown below - where R1 would be Rjb and R2 is Rjc. Then recalculate DeltaT. The temperature of the PCB is measured right next to the controller - with in a few mm - per the JEDEC test specification.
CFD Simulation two resistor:
Solve above for kcond for the top and bottom of the IC.
Then apply this conductivity the each part of the IC.
The controller is 2.54 x 2.54 x 2 thick. So each half will be 1 mm thick.
k = deltaX/ A R
k for the top = 93.9 W/K m
k for the bottom = 4.19
Make solid materials (in the engineering data base) with the conductivity above and apply to each part of the controller.
Make a temperature goal at the interface the average temperature (this is junction).
The 2° from the lab test is measured where? If the top of the controller case is 2°C hotter than the air the power values are way lower.
This is a switching power supply controller. The power going into the controller IS NOT the power dissipated in the controller. You need the resistance of the TEC. There are efficiency curves on page 8 of the data sheet that allow you to estimate the efficiency and the power dissipation in the controller. The if you simply want to estimate the power loss in the controller, measure the voltage and current across the TEC, measure the supply voltage and current at the ADN8834 and the difference is the power lost in the controller. This is a slight over estimate since there will also be power lost in the external inductor, output cap, pc board traces, etc. MOST of the difference, though, is the power lost in the controller.
Thank you for the technical references. Wrt your suggestions,
#1) I calculated the overall resistance in parallel with the formula provided as
R = (1/(1/1.65)+(1/37))
R = 1.58 C/W
with this resistance the DeltaT is calculated as 1.42 degree Celcius, which is very much near to the actual temperature raise. But here i am unclear on how could I model this in the flow simulation.
#2) The controller which we are using is of Quad flat type whose dimensions is 4x4x0.75 (in mm), hence I divided it into 2 parts of equal thicknesses (0.375 mm) and computed the conductivity as,
k = deltaX/ A R
k for the top = 14.2 W/mK
k for the bottom = 0.633 W/mK
created new materials with the above parameters and conducted simulation, but still the temp raise was around 85 C (for 0.9 W).
Can you attach your model? If natural convection you will need a large computational domain - say 20 x the board height around the PCB.
Hello Mark & Lawrence,
Thank you for your Input. It gave me an insight on different aspects of consideration. But I am still confused, as I have received two completely different ways of approach.
There is a change in the power supplied. The actual power supplied is found to be 0.9 W (and not 2.6 W as previously mentioned). But still with 0.9 W, the temperature raise is in the range of 85 degrees celcius which is way more than the actual temperature measured (2 degree celcius).
I was the designer of this part at Analog Devices. I'm curious what current and voltage levels you are measuring. I'd like to know the supply voltage to the adn8833/34,
a. the voltage at LFB pin with respect to PVIN_L and PGND_L (assuming you are using an LFCSP).
b. If you are using the WLCSP, then the voltage at the LFB pin with respect to PVIN and PGND_L.
2. The resistance of the TEC at the current it is operating.
3. The voltage across the TEC.
4. The PVIN voltage with respect to the PGND voltage (measure these as close to the part as possible).
5. The voltage at the SFB pin.
6. The operating frequency.
The heating in the wafer level package will generally be more severe because the heat flow is through the solder bumps to the PCB board. The LFCSP places the die on an exposed thermal paddle so the heat flow in this package is more efficient.
I'm also curious about the power losses in the inductor. Those will be mostly resistive rather than core losses. It will be helpful if you provide an accurate measurement of the inductor resistance so it is possible to remove the RMS switching losses from the power dissipation estimate at the ADN8833/34.
I'd like to do my own estimate of what the power dissipation at the part is.
are they in contact? Why not use a two resistor model (I think you need the electronic cooling package for this). If there is a small ap then the resistance will be quite high.
The electronics cooling module uses the two resistor method as a solution. I have tested a hand-made and an electronics cooling library two-resistor-part and both give the same result. The electronics module just eliminates a few clicks. The electronics module gives you some efficiency but NO computational capability.
I am pretty aware of what the package does and does not do and yes you can do most things manually but there are a few things like Joule heating that are not available in the base package - you might be able to approximate this as well, I haven't tried as I own the module.
Such a large discrepancy between test and simulation says to me that there is a modelling error. Further the heat is not able to get out of the part as easily as expected hence the temperature rise. Obviously the path thru the board is not what it should be. If this were me and i wanted to sort this out I would do a natural convection sim of just the chip and see what i get for a temp rise as then you know what that is. Then I would put the power on a surface patch on the board and see what that does. Some insight should be provided by those two sims as to where the problem is.
The multilayer PCB representations have limitations that are not necessarily clear in the documentation. I've found that they don't accurately represent component-to-board contact. When you enter your description of the copper layers and board thickness, etc... the electronics module calculates bulk conductivities in both axes as if they were equal throughout the board. The bulk conductivities are significantly lower than that of the top copper layer that your component is contacting. Its a similar result to what you could expect if you had your component contacting the solder mask. The outer copper layer in reality will act as a heat spreader.
You could try modeling the outer copper layers, and cap off the PCB with that. You then need to adjust the PCB layers description accordingly. Subtract the copper layers you've discretely modeled, and the thickness of the copper too. If you have a component on top and contact with a heat sink on the bottom, then you'd need to model both the top and bottom copper layers. Otherwise just the component side should be enough.
If the board design needs to be optimized for thermal performance you may need to include those details in your simulation. For example, if thermal vias will be needed to get the heat through the board, then you'll need to model the thermal vias.
The vias can be modeled in aggregate. That is cut a square hole under the component and fill it with a copper slug to represent all the vias. I suspect the modeling each layer and each via will be a chore and meshing issue.